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CYNSE70032-83BGC Datasheet(PDF) 53 Page - Cypress Semiconductor

Part # CYNSE70032-83BGC
Description  Network Search Engine
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE70032-83BGC Datasheet(HTML) 53 Page - Cypress Semiconductor

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CYNSE70032
Document #: 38-02042 Rev. *E
Page 53 of 126
The 136-bit word K (presented on the DQ bus in cycles A and B of the command) is also stored in the even and odd comparand
registers specified by the Comparand Register Index in the command’s cycle B. In ×136 configurations, the even and odd
comparand register can subsequently be used by the Learn command in only one of the devices (the first non-full device). The
word K (presented on the DQ bus in cycles A and B of the command) is compared to each entry in the table, starting at location 0.
The first matching entry’s location address L is the winning address that is driven as part of the SRAM address on the SADR[21:0]
lines (see “SRAM Addressing” on page 98). The global winning device will drive the bus in a specific cycle. On global miss cycles,
the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving device for SSF and
SSV signals) will be the default driver for such missed cycles. Note. During 136-bit searches of 136-bit-configured tables, the
Search hit will always be at an even address.
The Search command is a pipelined operation and executes a Search at half the rate of the CLK2X frequency for 136-bit searches
in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search command cycle
(two CLK2X cycles) is shown in Table 13-12.
For one to eight devices in the table and TLSZ = 01, Search latency from command to SRAM access cycle is 5. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-13.
Table 13-12. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
8K × 136 bits
4
1–8 (TLSZ = 01)
64K × 136 bits
5
1–31 (TLSZ = 10)
248K × 136 bits
6
Table 13-13. Shift of SSF and SSV from SADR
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
CFG = 01010101
135
0
Location
0
2
4
6
131070
(136-bit configuration)
address
K
GMR
Comparand Register (odd)
Comparand Register (even)
A
B
135
0
67
0
(First matching entry)
L
A
B
Even
Odd
Will be same in each of the eight
devices
Must be same in each of the eight
devices
Figure 13-30. ×136 Table with Eight Devices


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