CYNSE70032
Document #: 38-02042 Rev. *E
Page 31 of 126
the command) is compared with each entry in the table, starting at location 0. The first matching entry’s location address L is the
winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98). The
global winning device will drive the bus in a specific cycle. On a global miss cycle the device with LRAM = 1 (default driving device
for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in Table 13-4.
Search latency from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ = 01). SSV and SSF also
shift further to the right for different values of HLAT as specified in Table 13-5.
13.3
68-bit Search on Tables Configured as ×68 Using up to 31 CYNSE70032 Devices
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 13-9. Each of the four blocks in the diagram
represents eight CYNSE70032 devices (except the last, which has seven devices). The diagram for a block of eight devices is
shown in Figure 13-10. The following are the parameters that are programmed into the 31 devices.
• First thirty devices (devices 0–29): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1.
Note
. All devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table (device
number 30 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 29
in this case) must be programmed with LRAM = 0 and LDEV = 0.
Table 13-4. Search latency from Instruction to SRAM Access Cycle
Number of Devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
16K × 68 bits
4
1–8 (TLSZ = 01)
128K × 68 bits
5
1–31 (TLSZ = 10)
496K × 68 bits
6
Table 13-5. Shift of SSF and SSV from SADR
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
CFG = 00000000
67
0
Location
1
2
3
131071
(68-bit configuration)
address
K
GMR
Comparand Register (Odd)
Comparand Register (Even)
K
K
67
0
67
0
(First matching entry)
L
Must be same in each of the eight
devices
Will be the same in each of the eight
devices
0
Figure 13-8. ×68 Table with Eight Devices
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