CYNSE70032
Document #: 38-02042 Rev. *E
Page 30 of 126
The following is the sequence of operation for a single 68-bit Search command (also refer to “Command and Command Param-
eters,” Subsection 12.2 on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) to CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same
bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to be compared.
The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and to apply Search command (10) on CMD[1:0]. CMD[5:2] must be
driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A and
B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry
and hit flag (see page 14 for a description of SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared.
Note
. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B. The even
and odd GMR pairs selected for the comparison must also be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 13-8. The entire table of eight devices of 68-bit entries is compared to a
68-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and local mask bits. The effective
GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and selected
by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the command)
is also stored in both even and odd comparand register pairs (selected by the Comparand Register Index in command cycle B)
in each of the eight devices. In the ×68 configuration, only the even comparand register can subsequently be used by the Learn
command in one of the devices (the first non-full device only). The word K (presented on the DQ bus in both cycles A and B of
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
CMD[8:2]
Search2
Search4
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
CFG = 00000000, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
PHS_L
SADR[21:0]
SSF
SSV
Search1
Search2
Search3
D1
D2
D3
D4
01
01
01
01
Search1
Search3
A B A B A B A B
A4
0
|(LHI[6:0])
LHO[1:0]
0
z
0
0
z
0
ALE_L
WE_L
1z
1
0
z
1
0
0
z
1
0
Search4
(Global
winner.)
z
(Miss on
this device.)
(Miss on
this device.)
(Local but
not global
winner.)
Figure 13-7. Timing Diagram for 68-bit Search Device Number 7 (Last Device)
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