CYNSE70032
Document #: 38-02042 Rev. *E
Page 25 of 126
The following is the sequence of operation for a single 68-bit Search command (also refer to “Command and Command Param-
eters,” Subsection 12.2 on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven by the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same
bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to be compared.
The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and to apply Search command (10) on CMD[1:0]. CMD[5:2] must be
driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A and
B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry
and the hit flag (see page 14 for information on SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared.
Note
. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B. The even
and odd GMR pairs selected for the compare must be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 13-3. The entire table of 68-bit entries is compared to a 68-bit word K
(presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective GMR
is the 68-bit word specified by the identical value in both even and odd GMR pairs selected by the GMR Index in the command’s
cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both even and
odd comparand register pairs selected by the Comparand Register Index in the command’s cycle B. In a ×68 configuration, only
the even comparand register can subsequently be used by the Learn command. The word K (presented on the DQ bus in both
cycles A and B of the command) is compared with each entry in the table, starting at location 0. The first matching entry’s location
address L is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing”
on page 98).
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (which is two CLK2X cycles) is shown in Table 13-1.
LHO[0]
65
4321
0
LHI
LHO[1]
BHI[2:0]
DQ[67:0]
SRAM
CYNSE70032
CMDV, CMD[8:0]
BHI[2:0]
SSF, SSV
Figure 13-2. Hardware Diagram for a Table with a Single Device
CFG = 00000000
67
0
Location
0
1
2
3
16383
(68-bit configuration)
address
K
GMR
Comparand Register (odd)
Comparand Register (even)
K
K
67
0
67
0
(First matching entry)
L
Figure 13-3. ×68 Table with One Device
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