CYNSE70032
Document #: 38-02042 Rev. *E
Page 21 of 126
The read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the
ADR and the BLEN before initiating a burst Read command.
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied
on the DQ bus as shown in Table 12-6. The host ASIC selects the CYNSE70032 device where ID[4:0] matches the DQ[25:21]
lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 device with the LDEV bit set.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus, and drives ACK and EOT from Z to low.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus and drives the ACK signal
high.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the BLEN field of the RBURREG are complete.
On the last transfer, the CYNSE70032 device drives the EOT signal high.
• Cycle (4 + 2n): The selected device drives the DQ[67:0] to a three-state condition, and drives the ACK and EOT signals low.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to a three-state condition. The burst Read instruction
is complete, and a new operation can begin. Table 12-6 describes the Read address format for data and mask arrays for burst
Read operations.
12.4
Write Command
The Write command can be a single Write of a data array, mask array, register, or an external SRAM location (CMD[2] = 0). It
can also be a burst Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask
array locations. A single-location Write is a three-cycle operation as shown in Figure 12-3. The burst Write adds one extra cycle
for each successive location Write.
Table 12-5. Read Address Format for Internal Registers
DQ[67:26]
DQ[25:21]
DQ[20:19]
DQ[18:6]
DQ[5:0]
Reserved
ID
11: Register
Reserved
Register Address
Table 12-6. Read Address Format for Data and Mask Arrays
DQ[67:26] DQ[25:21]
DQ[20:19]
DQ[18:14]
DQ[13:0]
Reserved
ID
00: Data Array
Reserved Do not care. These fifteen bits come from the internal RBURADR, which
increments for each access.
Reserved
ID
01: Mask Array Reserved Do not care. These fifteen bits come from the internal RBURADR, which
increments for each access.
CMDV
CMD[1:0]
ACK
EOT
DQ
FF
FF
Data1
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
cycle
11
cycle
12
Data0
Data2
FF
Data3
FF
PHS_L
CMD[8:2]
Address
A B
Read
CLK2X
Figure 12-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
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