CYNSE70032
Document #: 38-02042 Rev. *E
Page 18 of 126
11.0
Data and Mask Addressing
Figure 11-1 shows CYNSE70032 data and mask array addressing.
12.0
Commands
A master device such as an ASIC controller issues commands to the CYNSE70032 device using the command valid (CMDV)
signal and the CMD bus. The following subsections describe the operation of the commands.
12.1
Command Codes
The CYNSE70032 device implements four basic commands, shown in Table 12-1. The command code must be presented to
CMD[1:0] while keeping the CMDV signal high for two CLK2X cycles (cycles A and B). The controller ASIC must align the
instructions using the PHS_L signal. The CMD[8:2] field passes the parameters of the command in cycles A and B.
Table 12-1. Command Codes
Command Code
Command
Description
00
Read
Reads one of the following: data array, mask array, device registers, or external SRAM.
01
Write
Writes one of the following: data array, mask array, device registers, or external SRAM.
10
Search
Searches the data array for a desired pattern using the specified register from the GMR
array and local mask associated with each data cell.
11
Learn
The device has internal storage for up to 16 comparands that it can learn. The device
controller can insert these entries at the next free address (as specified by the NFA
register) using the Learn instruction.
2 K
136
4 K
68
4 K
68
1 K
272
Figure 10-2. Multiwidth Database Configurations
CFG = 10010000
CFG = 00000000
CFG = 10101010
67
0
68
0
1
2
3
16383
283
0
68
68
3
2
1
0
7
6
5
4
16380
16381
16382
16383
68
68
CFG = 01010101
135
0
68
68
1
0
3
2
5
4
7
6
16382
16383
(68-bit configuration)
(272-bit configuration)
(136-bit configuration)
16K
4K
64K
Figure 11-1. Addressing CYNSE70032 Data and Mask Arrays
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