CYNSE70032
Document #: 38-02042 Rev. *E
Page 17 of 126
10.0
NSE Architecture and Operation Overview
The CYNSE70032 device consists of 16K × 68-bit storage cells referred to as data bits. There is a mask cell corresponding to
each data cell. Figure 10-1 shows the three organizations of the device based on the value of the CFG bits in the command
register.
During a Search operation, the Search data bit (S), the data array bit (D), the mask array bit (M), and the global mask bit (G) are
used in the following manner to generate a match at that bit position (see Table 10-1). The entry with a match on every bit position
results in a successful Search during a Search operation.
In order for a successful Search to make the device the local winner in the Search operation, all 68-bit positions within a device
must generate a match for a 68-bit entry in 68-bit-configured quadrants, or all 136-bit positions must generate a match for two
consecutive even and odd 68-bit entries in quadrants configured as 136 bits, or all 272-bit positions must generate a match for
four consecutive entries aligned to four entry-page boundaries of 68-bit entries in quadrants configured as 272 bits.
An arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a Search
cycle. The global winning device drives the SRAM bus, SSV, and the SSF signals. In the case of a Search failure, the device(s)
with LDEV and LRAM bits set drive the SRAM bus, SSF, and SSV signals.
The CYNSE70032 device can be configured to contain tables of different widths, even within the same chip. Figure 10-2 shows
a sample configuration of different widths.
Table 10-1. Bit Position Match
GM
D
S
Match
0X
X
X
1
10
X
X
1
11
001
11
100
11
010
11
111
Data
8 K
136
Data
Masks
4 K
272
CFG = 01010101
CFG = 10101010
16K
68
CFG = 00000000
Masks
Figure 10-1. CYNSE70032 Database Width Configuration
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