CYNSE70032
Document #: 38-02042 Rev. *E
Page 14 of 126
7.2
Mask Registers
The device contains sixteen 68-bit global mask registers (eight pairs) dynamically selected in every Search operation to select
the search subfield. The addressing of these registers is explained in Figure 7-2. The three-bit GMR Index supplied on the CMD
bus can apply eight pairs of global masks during the Search and Write operations, as shown below. Note. In 68-bit Search and
Write operations, the host ASIC must program both the even and odd mask registers with the same values.
Each mask bit in the GMRs is used during Search and Write operations. In Search operations, setting the mask bit to 1 enables
compares; setting the mask bit to 0 disables compares (forced match) at the corresponding bit position. In Write operations to
the data or mask array, setting the mask bit to 1 enables writes; setting the mask bit to 0 disables writes at the corresponding bit
position.
7.3
Search Successful Registers (SSR[0:7])
The device contains eight SSRs to hold the index of the location where a successful search occurred. The format of each register
is described in Table 7-2. The Search command specifies which SSR stores the index of a specific Search command in cycle B
of the Search instruction. Subsequently, the host ASIC can use this register to access that data array, mask array, or external
SRAM using the index as part of the indirect access address (see Table 7-2 and Table 8-1). The device with a valid bit set performs
a Read or Write operation. All other devices suppress the operation.
8.0
Command Register
Table 8-1 describes the command register fields.
Table 7-2. Search Successful Register Description
Field
Range
Initial Value
Description
INDEX
[13:0]
X
Index. This is the address of the 68-bit entry where a successful Search occurs. The device
updates this field only when the Search is successful. If a hit occurs in a 136-bit entry-size
quadrant, the least significant bit (LSB) is 0. If a hit occurs in a 272-bit entry-size quadrant,
the two LSBs are 00. This index updates if the device is either a local or global winner in
a Search operation.
–
[30:14]
0
Reserved.
VALID
[31]
0
Valid. During a Search operation in a depth-cascaded configuration, the device that is a
global winner in a match sets this bit to 1. It updates only when the device is a global winner
in a Search operation.
–
[67:32]
0
Reserved.
Table 8-1. Command Register Description
Field
Range
Initial Value
Description
SRST
[0]
0
Software Reset. If 1, this bit resets the device with the same effect as a hardware reset.
Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically
resets to 0 after the reset has completed.
DEVE
[1]
0
Device Enable. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and ALE_L),
SSF, and SSV signals in a three-state condition and forces the cascade interface output
signals LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose
of this bit is to make sure that there are no bus contentions when the devices power up
in the system.
001
123
245
367
489
510
11
612
13
714
15
Index
135
68
68
Search and Write Command Global Mask Selection
0
Figure 7-2. Addressing the Global Mask Register Array
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