CYNSE70032
Document #: 38-02042 Rev. *E
Page 100 of 126
15.4
SRAM Read with a Table of up to Eight Devices
The following explains the SRAM Read operation completed through a table of up to eight devices using the following parameter:
TLSZ = 01. Figure 15-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved
through CYNSE70032 device number 0. Figure 15-3 and Figure 15-4 show timing diagrams for device number 0 and device
number 7, respectively.
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. During this cycle the host ASIC also supplies SADR[21:19] on CMD[8:6].
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10 to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0].
• Cycle 5: The selected device continues to drive DQ[67:0] and drives ACK from high-Z to low.
• Cycle 6: The selected device drives the Read address on SADR[21:0]. It also drives ACK high, CE_L low, WE_L high, and
ALE_L low.
• Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and DQ bus in a three-state condition. It continues to drive ACK low.
At the end of cycle 7, the selected device floats ACK in a three-state condition, and a new command can begin.
cycle
CLK2X
DQ
Read
Address
ACK
OE_L
WE_L
ALE_L
SADR
Address
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1.
PHS_L
CMD[8:2]
A
B
z
z
0
1
0
z
z
0
0
1
z
1
z
1
SSV
0
0
SSF
CE_L
1
0
1
DQ driven by CYNSE70032.
CMDV
CMD[1:0]
Figure 15-1. SRAM Read ACCESS (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
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