CYNSE70032
Document #: 38-02042 Rev. *E
Page 10 of 126
3.0
Block Diagram
4.0
Functional Description
The following subsections contain the following descriptions: command (CMD) and DQ bus (command and databus), database
entry, arbitration logic, pipeline and SRAM control, and full logic.
4.1
Command Bus and DQ Bus
CMD[8:0] carries the command and its associated parameter. DQ[67:0] is used for data transfer to and from the database entries,
which is made up of data and mask fields that are organized as data and mask arrays. The DQ bus carries the Search data (of
the data and mask arrays and internal registers) during the Search command, as well as the address and data during Read or
Write operations. The DQ bus can also carry address information for the flow-through accesses to the external SRAMs or
SSRAMs.
4.2
Database Entry (Data Array and Mask Array)
Each database entry comprises a data and a mask field. The resultant value of the entry is “1,” “0,” or “X (don’t care),” depending
on the value in the data mask bit. The on-chip priority encoder selects the first matching entry in the database that is nearest to
location 0.
4.3
Arbitration Logic
When multiple search engines are cascaded to create large databases, the data being searched is presented simultaneously to
all search engines in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the search
engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the
SRAM bus.
Compare/PIO Data
DQ[67:0]
CMDV
CMD[8:0]
LHI[6:0]
Command
and PIO Access
CMD
Arbitration
Logic
LHO[1:0]
Pipeline
and
SRAM
Control
SADR[21:0]
OE_L
BHO[2:0]
SSF
WE_L
CE_L
ID[4:0]
BHI[2:0]
SSV
ACK
TAP
TAP
Controller
ALE_L
FULO[1:0]
FULI[6:0]
EOT
Full Logic
FULL
RST_L
PHS_L
Decode
Comparand Register Pairs [15:0]
Global Mask Register Pairs [7:0]
Information and Command Register
Burst Read Register
Burst Write Register
Next-free Address Register
Search Successful Index Registers [7:0]
CLK2X
[All registers are 68 bits wide.]
Configurable as
16K x 68
8K x 136
4K x 272
Mask Array
Configurable as
16K x 68
8K x 136
4K x 272
Data Array
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