98 / 126 page
CYNSE70032
Document #: 38-02042 Rev. *E
Page 98 of 126
15.0
SRAM Addressing
Table 15-1 describes the commands used to generate addresses on the SRAM address bus. The index[13:0] field contains the
address of a 68-bit entry that results in a hit in 68-bit-configured partition. It is the address of the 68-bit entry that lies at the 136-bit
page, and the 272-bit page boundaries in 136-bit- and 272-bit-configured quadrants, respectively.
Section 7.0, “Registers” on page 13 of this specification, describes the NFA and SSR registers. ADR[13:0] contains the address
supplied on the DQ bus during PIO access to the CYNSE70032. Command bits 8, and 7 {CMD[8:6]} are passed from the
command to the SRAM address bus. See Section 12.0, “Commands” on page 18, for more information. ID[4:0] is the ID of the
device driving the SRAM bus (see Section 21.0, “Pinout Descriptions and Package Diagrams” on page 120, for more information).
FULO[0]
654
3
2
1
0
FULI
FULO[0]
65
4
3
2
1
0
FULI
FULO[1]
65
4
3
2
1
0
FULI
FULO[0]
65
4
3
2
1
0
FULI
FULO[0]
6
5
43
21
0
FULI
FULO[0]
65
4
32
1
0
FULI
6
5
4
32
1
0
FULI
65
4
3
210
FULO[0]
FULI
FULI
FULI
FULO[1]
FULO[1]
FULO[1]
DQ[67:0]
FULO[1] FULO[0]
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
VDDQ
CYNSE70032
CYNSE70032
CYNSE70032
CYNSE70032
CYNSE70032
CYNSE70032
CYNSE70032
CYNSE70032
FULI
FULO[0]
Figure 14-3. FULL Generation in a Cascaded Table
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