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CYNSE70032
Document #: 38-02042 Rev. *E
Page 96 of 126
At the end of cycle 2, a new instruction can begin. SRAM Write latency is the same as the Search to the SRAM read cycle (it is
measured from the second cycle of the Learn instruction).
14.0
Depth-Cascading
The search engine application can depth-cascade the devices to various table sizes of different widths (68 bits, 136 bits, or 272
bits). The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. Search latency increases
as table size increases; the Search rate itself remains constant.
14.1
Depth-Cascading up to Eight Devices (One Block)
Figure 14-1 shows how up to eight devices can be cascaded to form 256K × 68-bit, 128K × 136-bit, or 64K × 272-bit tables. It
also shows the interconnection between devices for depth-cascading. Each search engine asserts LHO[1] and LHO[0] signals
to inform downstream devices of its results. The LHI[6:0] signals for a device are connected to LHO signals of the upstream
devices. The host ASIC must program the TLSZ to 01 for each of up to eight devices in a block. A single device alone drives the
SRAM bus in any single cycle.
LHO[0]
LHO[0]
65
4321
0
LHI
LHO[0]
65
32
10
LHI
LHO[1]
6
543
2
1
0
LHI
LHO[0]
6
54321
0
LHI
LHO[0]
65
4
3
2
1
0
LHI
LHO[0]
65
4
32
1
0
LHI
LHO[0]
65
4
32
10
LHI
BHO[0]
65
4
32
1
0
LHI
LHI
LHI
LHI
LHO[1]
LHO[1]
LHO[1]
BHO[1]
BHO[0]
BHO[1]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
DQ[67:0]
SRAM
LHO[1] LHO[0]
CYNSE70032 #0
CYNSE70032 #1
CYNSE70032 #2
CYNSE70032 #3
CYNSE70032 #4
CYNSE70032 #5
CYNSE70032 #6
CYNSE70032 #7
4
BHO[2]
BHO[2]
CMDV
CMD[8:0]
SSF, SSV
Figure 14-1. Depth-Cascading to Form a Single Block
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