95 / 126 page
CYNSE70032
Document #: 38-02042 Rev. *E
Page 95 of 126
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
of the comparand register pair that will be written to the data array in the 136-bit-configured table. For a Learn in a 68-bit-con-
figured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven
on SADR[21:19] in the SRAM Write cycle.
• Cycle 1B: The host ASIC continues to drive CMDV to 1, CMD[1:0] to 11, and CMD[5:2] with the comparand pair index. CMD[6]
must be set to 0 if the Learn is being performed on a 68-bit-configured table, and to 1 if the Learn is being performed on a
136-bit-configured table.
• Cycle 2: The host ASIC drives CMDV to 0.
Table 13-25. SRAM Write Cycle Latency from Second Cycle of Learn Instruction
Number of Devices
Latency in CLK Cycles
1 (TLSZ = 00)
4
1–8 (TLSZ = 01)
5
1–31 (TLSZ = 10)
6
cycle
Learn1
Learn2
CLK2X
CMDV
CMD[1:0]
DQ
SADR[21:0]
CE_L
CMD[8:2]
X
WE_L
OE_L
X
XXX
X
TLSZ = 01, LRAM = 1, LDEV = 1.
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
X
X
X
1A 1B
Comp1
Comp2
X
PHS_L
1
1
z
z
z
z
z
0
zz
zz
0
0
SSV
SSF
1
1
1
0
z
1
1
Figure 13-71. Learn Timing Diagram on Device Number 7 (TLSZ = 01)
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
