CYNSE70032
Document #: 38-02042 Rev. *E
Page 77 of 126
Note
. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the HIT/MISS assumptions defined in Table 13-22. For the purpose
of illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. Figure 13-55
shows the timing diagram for a Search command in the 272-bit-configured table consisting of 31 devices for each of the eight
devices in block number 0. Figure 13-56 shows the timing diagram for a Search command in the 272-bit-configured table of 31
devices for all devices above the winning device in block number 1. Figure 13-57 shows the timing diagram for the globally winning
device (the final winner within its own and all blocks) in block number 1. Figure 13-58 shows the timing diagram for all the devices
below the globally winning device in block number 1. Figure 13-59, Figure 13-60, and Figure 13-61, respectively, show the timing
diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning
device for block number 2. Figure 13-62, Figure 13-63, Figure 13-64, and Figure 13-65, respectively, show the timing diagrams
of the device above the globally winning device, the globally winning device, the devices below the globally winning device (except
device 30), and last device (device 30) for block number 3.
The 272-bit Search operation is pipelined and executes as follows. Four cycles from the last cycle of the Search command each
of the devices knows the outcome internal to it for that operation. In the fifth cycle from the Search command, the devices in a
block (less than or equal to eight devices resolving the winner within them using an LHI[6:0] and LHO[1:0] signalling mechanism)
arbitrate for a winner. In the sixth cycle after the Search command, the blocks of devices resolve the winning block through a
BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for the
Search operation.
Table 13-22. Hit/Miss Assumptions
Search Number
1
2
3
Block 0
Miss
Miss
Miss
Block 1
Miss
Miss
Hit
Block 2
Miss
Hit
Hit
Block 3
Hit
Hit
Miss
BHO[2]
Block of 8 CYNSE70032s block 0 (devices 0–7)
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
Block of 7 CYNSE70032s block 3 (devices 24–30)
BHI[1]
BHI[0]
GND
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70032s block 1 (devices 8–15)
Block of 8 CYNSE70032s block 2 (devices 16–23)
DQ[67:0]
SRAM
BHO[2]
BHO[2]
BHO[1]
BHO[1]
BHO[0]
BHO[0]
CMD[8:0], CMDV
SSF, SSV
Figure 13-53. Hardware Diagram for a Table with 31 Devices
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