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CYNSE70032
Document #: 38-02042 Rev. *E
Page 57 of 126
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
CMD[8:2]
Search2
Search4
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
PHS_L
SADR[21:0]
SSF
SSV
ALE_L
Search1
Search2
Search4
D1
D2
D3
D4
01
01
01
01
Search1
Search3
A B A B A B A B
z
z
z
z
z
z
z
LHO[1:0]
0
I(BHI[2:0])
0
Search3
|(LHI[6:0])
0
BHO[2:0]
0
(Miss on
this device.)
(Miss on
this device.)
(Miss on
this device.)
(Miss on
this device.)
Figure 13-33. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
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