CYNSE70032
Document #: 38-02042 Rev. *E
Page 47 of 126
Note
. For 136-bit searches, the host ASIC must supply two distinct 68-bit data words on DQ[67:0] during cycles A and B. The
even-numbered GMR of the pair specified by the GMR Index is used for masking the word in cycle A. The odd-numbered GMR
of the pair specified by the GMR Index is used for masking the word in cycle B.
The logical 136-bit search operation is shown in Figure 13-25. The entire table of 136-bit entries is compared to a 136-bit word K
(presented on the DQ bus in cycles A and B of the command) using the GMR and local mask bits. The GMR is the 136-bit word
specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A. The 136-bit word K
(presented on the DQ bus in cycles A and B of the command) is also stored in both even and odd comparand register pairs
selected by the Comparand Register Index in the command’s cycle B. The two comparand registers can subsequently be used
by the Learn command with the even comparand register stored in an even location, and the odd comparand register stored in
an adjacent odd location. The word K (presented on the DQ bus in cycles A and B of the command) is compared with each entry
in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the
SRAM address on SADR[21:0] lines (see “SRAM Addressing” on page 98). Note. The matching address is always going to be
an even address for a 136-bit Search.
The Search command is a pipelined operation that executes searches at half the rate of the frequency of CLK2X for 136-bit
searches in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search
command cycle (two CLK2X cycles) is shown in Table 13-9.
For a single device in the table with TLSZ = 00, the Search latency from command to SRAM access cycle is 4. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-10.
Table 13-9. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
8K × 136 bits
4
1–8 (TLSZ = 01)
64K × 136 bits
5
1–31 (TLSZ = 10)
248K × 136 bits
6
Table 13-10. Shift of SSF and SSV from SADR
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
CFG = 01010101
135
0
Location
0
2
4
6
16382
(136-bit configuration)
address
K
GMR
Comparand Register (odd)
Comparand Register (even)
A
B
135
0
67
0
(First matching entry)
L
A
B
Even
Odd
Figure 13-25. ×136 Table with One Device
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