CYNSE70032
Document #: 38-02042 Rev. *E
Page 45 of 126
by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in cycles A and B of the command)
is also stored in both even and odd comparand register pairs in each of the eight devices (and selected by the Comparand
Register Index in command’s cycle B). In the x68 configuration, the even comparand register can subsequently be used by the
Learn command, but only in the first non-full device. The word K (presented on the DQ bus in cycles A and B of the command)
is compared with each entry in the table, starting at location 0. The first matching entry’s location address L is the winning address
that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98). The global winning
device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 and LDEV = 1 will be the default
driver for such missed cycles.
The Search command is a pipelined operation and executes a search at half the rate of the frequency of CLK2X for 68-bit searches
in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command cycle (two
CLK2X cycles) is shown in Table 13-7.
For up to 31 devices in the table (TLSZ = 10), search latency from command to SRAM access cycle is 6. In addition, SSV and
SSF shift further to the right for different values of HLAT as specified in Table 13-8.
13.4
136-bit Search on Tables Configured as ×136 Using a Single CYNSE70032 Device
Figure 13-23 shows the timing diagram for a Search command in the 136-bit-configured table (CFG = 01010101) consisting of a
single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, LDEV = 1. The hardware diagram for this Search
subsystem is shown in Figure 13-24.
Table 13-7. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
16K × 68 bits
4
1–8 (TLSZ = 01)
128K × 68 bits
5
1–31 (TLSZ = 10)
496K × 68 bits
6
Table 13-8. Shift of SSF and SSV from SADR
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
CFG = 00000000
67
0
Location
0
1
2
3
507903
(68-bit configuration)
address
K
GMR
Comparand Register (odd)
Comparand Register (even)
K
K
67
0
67
0
(First matching entry)
L
Must be same in each of the eight
devices
Will be same in each of the eight
devices
Figure 13-22. ×68 Table with 31 Devices
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