DS1077L

16 of 21

NOTES:

1) All voltages are referenced to ground.

2) 4.87kHz is obtained from a -40MHz standard part.

3) Output voltage swings may be impaired at high frequencies combined with high output loading.

4) After this period, the first clock pulse is generated.

SCL signal.

then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data

10) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 3 preconditioning with

preconditioning consists of a 24hr +125°C storage bake, 192hr moisture soak at +30°C/60% R.H., and

three solder reflow passes.

TIMING DIAGRAM

SU:STO

t

HD:STA

t

SU:DAT

t

R

t

t

LOW

SCL

START

SDA

STOP

REPEATED

START

ORDERING INFORMATION:

DS1077L

Master Frequency (MHz)

40, 50, 60, 66.66

PACKAGE TYPE:

Z = SO (150MIL)

U = µSOP