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MPC7448ECS02AD Datasheet(PDF) 5 Page - NXP Semiconductors |
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MPC7448ECS02AD Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 8 page ![]() MPC7448 Hardware Specifications Addendum for the MC7448Txxnnnnmx Series, Rev. 2 Freescale Semiconductor 5 General Parameters 5.3 Voltage and Frequency Derating To reduce power consumption, these devices support voltage and frequency derating in which the core voltage (VDD) may be reduced if the reduced maximum processor core frequency requirements are observed. The supported derated core voltage, resulting maximum processor core frequency (fcore), and power consumption are provided in Table 11. Only those parameters in Table 11 are affected; all other parameter specifications are unaffected. Table 8. Clock AC Timing Specifications At recommended operating conditions. See Table 4. Characteristic Symbol Maximum Processor Core Frequency (MHz) Unit Notes 1000N 1267N 1400N 1700L Min Max Min Max Min Max Min Max Processor frequency DFS mode disabled fcore 500 1000 500 1267 500 1400 600 1700 MHz 1, 8, 9 Processor frequency DFS mode enabled fcore_DFS 250 500 250 633 250 700 300 850 MHz 10 VCO frequency fVCO 500 1000 500 1267 500 1400 600 1700 MHz 1, 9 Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus) frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:5] signal description in Section 9.1.1, “PLL Configuration,” in the hardware specifications for valid PLL_CFG[0:5] settings. 8. This reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (DFS) is disabled. fcore_DFS provides the maximum and minimum core frequencies in a DFS mode. 9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at the nominal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies must be reduced. See Section 5.3, “Voltage and Frequency Derating,” for more information. 10.This specification supports the Dynamic Frequency Switching (DFS) feature and is applicable only when one of the DFS modes (divide-by-2 or divide-by-4) is enabled. When DFS is disabled, the core frequency must conform to the maximum and minimum frequencies stated for fcore. Table 11. Supported Voltage, Core Frequency, and Power Consumption Derating Maximum Rated Core Frequency (Device Marking) Supported Derated Core Voltage (VDD) Maximum Derated Core Frequency (fcore) Full-Power Mode Power Consumption Typical Thermal Maximum 1000N N/A 1267N 1.0 V ± 50 mV 1000 MHz 6.0 W 7.3 W 8.5 W 1400N 1.0 V ± 50 mV 1000 MHz 8.0 W 9.9 W 11.5 W 1700L N/A |
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