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CLRC66103HNT Datasheet(PDF) 9 Page - NXP Semiconductors

Part # CLRC66103HNT
Description  High performance NFC frontend CLRC661 plus
Download  152 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC66103HNT Datasheet(HTML) 9 Page - NXP Semiconductors

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NXP Semiconductors
CLRC661
High performance NFC frontend CLRC661 plus
8 Functional description
001aam005
I2C,
LOGICAL
FIFO
512 Bytes
REGISTERS
STATEMACHINES
EEPROM
8 kByte
SPI
SAM interface
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
DVDD
POR
ADC
PLL
LFO
RX
OSC
TX
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
AVDD
RNG
ANALOGUE FRONT-END
BOUNDARY
SCAN
IF0
IFSEL0
IFSEL1
IF1
IF2
IF3
TCK
TDI
TMS
TDO
RESET
LOGIC
PDOWN
I2C
UART
SPI
host interfaces
INTERRUPT
CONTROLLER
IRQ
SIGIN
TIMER0..3
CRC
TIMER4
(WAKE-UP
TIMER)
SIGPRO
TX
CODEC
RX
DECOD
CL-
COPRO
SIGIN/
SIGOUT
CONTROL
SIGOUT
VMID RXN
RXP
TX1
TX2
XTAL1
XTAL2
SDA
SCL
VDD
VSS
PVDD
TVDD
TVSS
AUX1
AUX2
AVDD
DVDD
CLKOUT
Figure 3. Detailed block diagram of the CLRC661
8.1 Interrupt controller
The interrupt controller handles the enabling/disabling of interrupt requests. All of the
interrupts can be configured by firmware. Additionally, the firmware has possibilities to
trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0
and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En
and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt
controller register is implemented.
The CLRC661 indicates certain events by setting bit IRQ in the register Status1Reg and
additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the
host using its interrupt handling capabilities. This allows the implementation of efficient
host software.
Table 4. shows the available interrupt bits, the corresponding source and the condition
for its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in
register IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer
underflows.
CLRC661
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 3.7 — 23 June 2021
COMPANY PUBLIC
456937
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