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CLRC66103HNT Datasheet(PDF) 89 Page - NXP Semiconductors |
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CLRC66103HNT Datasheet(HTML) 89 Page - NXP Semiconductors |
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89 / 152 page  NXP Semiconductors CLRC661 High performance NFC frontend CLRC661 plus Bit Symbol Description 1 to 0 CollLevel Defines the strength of a signal to be interpreted as a collision: 0h - Collision has at least 1/8 of signal strength 1h - Collision has at least 1/4 of signal strength 2h - Collision has at least 1/2 of signal strength 3h - Collision detection is switched off Table 159. Rcv bits...continued 9.12.6 RxAna This register allows setting the gain (rcv_gain) and high pass corner frequencies (rcv_hpcf). Bit 7 6 5 4 3 2 1 0 Symbol VMid_r_sel RFU rcv_hpcf rcv_gain Access rights r/w - r/w r/w Table 160. RxAna register (address 39h) Bit Symbol Description 7, 6 VMid_r_sel Factory trim value, needs to be 0. 5, 4 RFU 3, 2 rcv_hpcf The rcv_hpcf [1:0] signals allow 4 different settings of the base band amplifier high pass cut-off frequency from ~40 kHz to ~300 kHz. 1 to 0 rcv_gain With rcv_gain[1:0] four different gain settings from 30 dB and 60 dB can be configured (differential output voltage/differential input voltage). Table 161. RxAna bits rcv_gain (Hex.) rcv_hpcf (Hex.) fl (kHz) fU (MHz) gain (dB20) bandwidth (MHz) 03 00 38 2.3 60 2.3 03 01 79 2.4 59 2.3 03 02 150 2.6 58 2.5 03 03 264 2.9 55 2.6 02 00 41 2.3 51 2.3 02 01 83 2.4 50 2.3 02 02 157 2.6 49 2.4 02 03 272 3.0 41 2.7 01 00 42 2.6 43 2.6 01 01 84 2.7 42 2.6 Table 162. Effect of gain and high-pass corner register settings CLRC661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.7 — 23 June 2021 COMPANY PUBLIC 456937 89 / 152 |
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