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CLRC66103HNT Datasheet(PDF) 71 Page - NXP Semiconductors |
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CLRC66103HNT Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 152 page  NXP Semiconductors CLRC661 High performance NFC frontend CLRC661 plus Bit Symbol Description 7 T1StopRx If set, the timer stops after receiving the first 4 bits. If cleared, the timer is not stopped automatically. Note: If LFO trimming is selected by T1start, this bit has no effect. 6 - RFU 5 to 4 T1Start 00b: The timer is not started automatically 01 b: The timer starts automatically at the end of the transmission 10 b: Timer is used for LFO trimming without underflow (Start/Stop on PosEdge) 11 b: Timer is used for LFO trimming with underflow (Start/Stop on PosEdge) 3 T1AutoRestart Set to logic 1, the timer automatically restarts its countdown from T1ReloadValue, after the counter value has reached the value zero. Set to logic 0 the timer decrements to zero and stops. The bit Timer1IRQ is set to logic 1 when the timer underflows. 2 - RFU 1 to 0 T1Clk 00 b: The timer input clock is 13.56 MHz 01 b: The timer input clock is 211,875 kHz. 10 b: The timer input clock is an underflow of Timer0 11 b: The timer input clock is an underflow of Timer2 Table 85. T1Control bits 9.7.2.6 T1ReloadHi High byte (MSB) reload value of the Timer1. Bit 7 6 5 4 3 2 1 0 Symbol T1ReloadHi Access rights r/w Table 86. T0ReloadHi register (address 15h) Bit Symbol Description 7 to 0 T1ReloadHi Defines the high byte reload value of the Timer 1. With the start event, the timer loads the value of the T1ReloadValHi and T1ReloadValLo. Changing this register affects the Timer only at the next start event. Table 87. T1ReloadHi bits 9.7.2.7 T1ReloadLo Low byte (LSB) reload value of the Timer1. Bit 7 6 5 4 3 2 1 0 Symbol T1ReloadLo Access rights r/w Table 88. T1ReloadLo register (address 16h) CLRC661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.7 — 23 June 2021 COMPANY PUBLIC 456937 71 / 152 |
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