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CLRC66103HNT Datasheet(PDF) 45 Page - NXP Semiconductors |
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CLRC66103HNT Datasheet(HTML) 45 Page - NXP Semiconductors |
45 / 152 page NXP Semiconductors CLRC661 High performance NFC frontend CLRC661 plus Address 0 (8) 1 (9) 2 (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 (F) 80 12 88 00 00 00 00 00 00 TxBitMod RFU TxDataCon TxDataMod TxSymFreq TxSym0H TySym0L TxSym1H 88 20 xx 04 50 40 00 00 00 TxSym1L TxSym2 TxSym3 TxSym10Le ngth TxSym32Le ngth TxSym32Bu rstCtrl TxSym10M od TxSym32M od 90 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x50 RxBitMod RxEOFSym RxSyncValH RxSyncValL RxSyncMod RxMod RXCorr FabCal 98 0x02 0x00 0x00 0x01 0x00 0x08 0x08 0xB2 Table 36. Register reset values (Hex.)(Page1 and page 2)...continued 8.8 Clock generation 8.8.1 Crystal oscillator The clock applied to the CLRC661 acts as time basis for generation of the carrier sent out at TX and for the quadrature mixer I and Q clock generation as well as for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has to be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. 001aam308 27.12 MHz XTAL1 XTAL2 READER IC Figure 28. Crystal connection Symbol Parameter Conditions Min Typ max Unit fxtal crystal frequency - 27.12 - MHz Δfxtal/fxtal relative crystal frequency variation -250 - +250 ppm ESR equivalent series resistance - 50 100 Ω CL load capacitance - 10 - pF Pxtal crystal power dissipation - 50 100 μW Table 37. Crystal requirements recommendations CLRC661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.7 — 23 June 2021 COMPANY PUBLIC 456937 45 / 152 |
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