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CLRC66103HNT Datasheet(PDF) 22 Page - NXP Semiconductors |
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CLRC66103HNT Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 152 page  NXP Semiconductors CLRC661 High performance NFC frontend CLRC661 plus For timing requirements, refer to Table 201. 8.4.4.2 I2C Data validity Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state or LOW state of the data line shall only change when the clock signal on SCL is LOW. 001aam300 data line stable; data valid change of data allowed SDA SCL Figure 13. Bit transfer on the I2C-bus 8.4.4.3 I2C START and STOP conditions To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined. A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH. A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is HIGH. The master always generates the START and STOP conditions. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. Therefore, the S symbol will be used as a generic term to represent both the START and repeated START (Sr) conditions. 001aam301 START condition S SCL SDA SCL SDA STOP condition P Figure 14. START and STOP conditions 8.4.4.4 I2C byte format Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB first, see Figure 14. The number of transmitted bytes during one data transfer is unrestricted but shall fulfill the read/write cycle format. CLRC661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.7 — 23 June 2021 COMPANY PUBLIC 456937 22 / 152 |
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