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TGA2752-SM,SAMPLE Datasheet(PDF) 9 Page - Qorvo, Inc |
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TGA2752-SM,SAMPLE Datasheet(HTML) 9 Page - Qorvo, Inc |
9 / 15 page TGA2752-SM 7.1 – 8.5 GHz Power Amplifier Data Sheet Rev. B, September 2020 | Subject to change without notice 9 of 15 www.qorvo.com © 2020 Qorvo US, Inc. All rights reserved. Confidential ® Pin Configuration and Description Top View Pad No. Label Description 1, 2, 3, 4, 6, 7, 8, 9,11, 13, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 27, 28, 29, 33, 34, 35, 37, 39, 41 NC No internal connection; can be grounded on PCB. 5 RF IN RF Input, matched to 50 Ω, AC Coupled. 10, 42 VG12 Gate voltage. Bias network is required; can be biased from either pin, and non- biased pin can be left open; see Application Circuit on page 11 as an example. 12, 40 VD1 Drain voltage; must be biased from both sides. Bias network is required; see Application Circuit on page 11 as an example. 14, 38 VD2 Drain voltage; must be biased from both sides. Bias network is required; see Application Circuit on page 11 as an example. 20, 32 VD3 Drain voltage; must be biased from both sides. Bias network is required; see Application Circuit on page 11 as an example. 26 RF OUT RF Output, matched to 50 ohms, AC Coupled. 30 VREF Reference diode output voltage. 31 VDET Detector diode output voltage. Varies with RF output power. 36 VG3 Gate voltage. Bias network is required; see Application Circuit on page 11 as an example. 43, 44, 45, 46, 47 GND Backside Paddle. Multiple vias should be employed to minimize inductance and thermal resistance; see Mounting Configuration on page 14 for suggested footprint. 2 5 4 3 1 8 7 6 9 10 11 12 13 14 15 16 17 18 19 20 21 29 26 27 28 30 23 24 25 22 42 41 40 39 38 37 36 35 34 33 32 31 47 43 44 45 46 |
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