MC13109A

23

MOTOROLA RF/IF DEVICE DATA

Figure 27. Test Mode Description

TM #

TM 3

TM 2

TM 1

TM 0

Counter Under Test or

Test Mode Option

“Tx VCO”

Input Signal

“Clk Out” Output Expected

0

0

0

0

0

Normal Operation

>200 mVpp

–

1

0

0

0

1

Rx Counter, upper 6

0 to 2.2 V

Input Frequency/64

2

0

0

1

0

Rx Counter, lower 8

0 to 2.2 V

See Note Below

3

0

0

1

1

Rx Prescaler

0 to 2.2 V

Input Frequency/4

4

0

1

0

0

Tx Counter, upper 6

0 to 2.2 V

Input Frequency/64

5

0

1

0

1

Tx Counter, lower 8

0 to 2.2 V

See Note Below

6

0

1

1

0

Tx Prescaler

>200 mVpp

Input Frequency/4

7

0

1

1

1

Reference Counter

0 to 2.2 V

Input Frequency/Reference Counter Value

8

1

0

0

0

Divide by 4, 25

0 to 2.2 V

Input Frequency/100

9

1

0

0

1

AGC Gain = 10 Option

N/A

–

10

1

0

1

0

AGC Gain = 25 Option

N/A

–

NOTE:

To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor

value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3

of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).

Test Modes

Test Mode Control latch bits enable independent testing of

internal counters and set AGC Gain Options. In test mode,

the “Tx VCO” input pin is multiplexed to the input of the

counter under test and the output of the counter under test is

multiplexed to the “Clk Out” output pin so that each counter

can be individually tested. Make sure test mode bits are set to

“0” for normal operation. Test mode operation is described in

Figure 27. During normal operation and when testing the Tx

Prescaler, the “Tx VCO” input can be a minimum of 200 mVpp

at 80 MHz and should be ac coupled. For other test modes,

input signals should be standard logic levels of 0 to 2.2 V and

a maximum frequency of 16 MHz.

Power–Up Defaults for Control and Counter Registers

When the IC is first powered up, all latch registers are

initialized to a defined state. The MC13109A is initially placed

in the Rx mode with all mutes active and nothing disabled.

The reference counter is set to generate a 5.0 kHz reference

frequency from a 10.24 MHz crystal. The MPU clock output

divider is set to 10 to give the minimum clock output

frequency. The Tx and Rx latch registers are set for USA

Channel Frequency #21. Figure 28 shows the initial

power–up states for all latch registers.

Figure 28. Latch Register Power–Up Defaults

MSB

LSB

Register

Count

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Tx

9965

–

–

1

0

0

1

1

0

1

1

1

0

1

1

1

0

Rx

7215

–

–

0

1

1

1

0

0

0

0

1

0

1

1

1

1

Ref

2048

–

–

0

0

1

0

0

0

0

0

0

0

0

0

0

0

Mode

N/A

–

0

0

0

0

1

1

0

1

1

1

0

1

1

1

1

Gain

N/A

–

–

–

–

–

–

–

–

–

–

–

1

0

1

0

0

TM

N/A

–

–

–

–

–

–

–

–

–

0

0

0

0

0

0

0