 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MC13109A Datasheet(PDF) 20 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
MC13109A Datasheet(HTML) 20 Page - Motorola, Inc |
|
|
20 / 28 page  MC13109A 20 MOTOROLA RF/IF DEVICE DATA “Clk Out” Divider Programming The “Clk Out” pin is derived from the 2nd local oscillator and can be used to drive a microprocessor, thereby reducing the number of crystals required. Figure 19 shows the relationship between the crystal frequency and the clock output for different divider values. Figure 20 shows the “Clk Out” register bit values. Figure 19. Clock Output Values Crystal Clock Output Divider Crystal Frequency 2 3 5 10 10.24 MHz 5.120 MHz 3.413 MHz 2.048 MHz 1.024 MHz 11.15 MHz 5.575 MHz 3.717 MHz 2.230 MHz 1.115 MHz 12.00 MHz 6.000 MHz 4.000 MHz 2.400 MHz 1.200 MHz Figure 20. Clock Output Divider Clk Out Bit #1 Clk Out Bit #2 Clk Out Divider Value 0 0 2 0 1 3 1 0 5 1 1 10 MPU “Clk Out” Power–Up Default Divider Value The power–up default divider value is “divide by 10”. This provides an MPU clock of about 1.0 MHz after initial power–up. The reason for choosing this relatively low clock frequency after intial power–up is that some microprocessors that operate down to a 2.0 V power supply have a maximum clock frequency of 1.0 MHz. After initial power–up, the MPU can change the clock divider value to set the clock to the desired operating frequency. Special care has been taken in the design of the clock divider to ensure that the transition between one clock divider value and another is “smooth” (i.e., there will be no narrow clock pulses to disturb the MPU). MPU “Clk Out” Radiated Noise on Circuit Board The clock line running between the MC13109A and the microprocessor has the potential to radiate noise which can cause problems in the system especially if the clock is a square wave digital signal with large high frequency harmonics. In order to minimize radiated noise, a 1.0 k Ω resistor is included on–chip in–series with the “Clk Out” output driver. A small capacitor can be connected to the “Clk Out” line on the PCB to form a single pole low pass filter. This filter will significantly reduce noise radiated from the “Clk Out” line. Volume Control The volume control can be programmed in 2.0 dB gain steps from –14 dB to 16 dB. The power–up default value is 0 dB. Figure 21. Volume Control Volume Control Bit #3 Volume Control Bit #2 Volume Control Bit #1 Volume Control Bit #0 Volume Control # Gain/Attenuation Amount 0 0 0 0 0 –14 dB 0 0 0 1 1 –12 dB 0 0 1 0 2 –10 dB 0 0 1 1 3 – 8.0 dB 0 1 0 0 4 – 6.0 dB 0 1 0 1 5 – 4.0 dB 0 1 1 0 6 – 2.0 dB 0 1 1 1 7 0 dB 1 0 0 0 8 2.0 dB 1 0 0 1 9 4.0 dB 1 0 1 0 10 6.0 dB 1 0 1 1 11 8.0 dB 1 1 0 0 12 10 dB 1 1 0 1 13 12 dB 1 1 1 0 14 14 dB 1 1 1 1 15 16 dB Gain Control Register The gain control register contains bits which control the Carrier Detect threshold. Operation of these latch bits are explained in Figures 22 and 23. MSB LSB 5–Bit CD Threshold Control Figure 22. Gain Control Latch Bits |
Similar Part No. - MC13109A |
|
Similar Description - MC13109A |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
