 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MC13109A Datasheet(PDF) 15 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
MC13109A Datasheet(HTML) 15 Page - Motorola, Inc |
|
|
15 / 28 page  MC13109A 15 MOTOROLA RF/IF DEVICE DATA ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C) Characteristic Unit Max Typ Min Symbol Measure Pin Condition PLL PIN INTERFACE EN to Clk Setup Time – EN, Clk tsuEC 200 – – ns Data to Clk Setup Time – Data, Clk tsuDC 100 – – ns Hold Time – Data, Clk th 90 – – ns Recovery Time – EN, Clk trec 90 – – ns Input Pulse Width – EN, Clk tw 100 – – ns Input Rise and Fall Time – Data Clk EN tr, tf – – 9.0 µs MPU Interface Power–Up Delay 90% of PLL Vref to Data, Clk, EN – tpuMPU – 100 – µs PLL LOOP 2nd LO Frequency – LO2 In LO2 Out fLO – – 12 MHz “Tx VCO” Input Frequency Vin = 200 mVpp Tx VCO ftxmax – – 80 MHz PLL I/O Pin Specifications The 2nd LO, Rx and Tx PLL’s and MPU serial interface are normally powered by the internal voltage regulator at the “PLL Vref” pin. The “PLL Vref” pin is the output of a voltage regulator which is powered from the “VCC Audio” power supply pin. Therefore, the maximum input and output levels for most PLL I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulated voltage at the “PLL Vref” pin. The ESD protection diodes on these pins are also connected to “PLL Vref”. Internal level shift buffers are provided for the pins (Data, Clk, EN, Clk Out) which connect directly to the microprocessor. The maximum input and output levels for these pins is VCC. Figure 5 shows a simplified schematic of the PLL I/O pins. Figure 5. PLL I/O Pin Simplified Schematics PLL Vref (2.2 V) In I/O VCC Audio (2.0 to 5.5 V) PLL Vref (2.2 V) VCC Audio (2.0 to 5.5 V) Clk Out Pin Data, Clk, and EN Pins LO2 In, LO2 Out, Rx PD, Tx PD and Tx VCO Pins Out 2.0 µA 1.0 k Ω Microprocessor Serial Interface The “Data”, “Clk”, and “EN” pins provide an MPU serial interface for programming the reference counters, the transmit and receive channel divider counter and various control functions. The “Data” and “Clk” pins are used to load data into the shift register. Figure 6 shows “Data” and “Clk” pin timing. Data is clocked on positive clock transitions. Figure 6. Data and Clock Timing Requirement Data, Clk, EN Data Clk tsuDC tr tf 50% 50% th 10% 90% After data is loaded into the shift register, the data is latched into the appropriate latch register using the “EN” pin. This is done in two steps. First, an 8–Bit address is loaded into the shift register and latched into the 8–Bit address latch register. Then, up to 16–Bits of data is loaded into the shift register and latched into the data latch register specified by the address that was previously loaded. Figure 7 shows the timing required on the EN pin. Latching occurs on the negative EN transition. |
Similar Part No. - MC13109A |
|
Similar Description - MC13109A |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
