MST703-LF datasheet(68/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 68 -

11/24/2010

Scaler Register (Bank=00, Registers B0h ~ FFh)

Index

Mnemonic

Bits

Description

CC_GAT

0

Comb Clock Gating.

1: Gating mode.

0: No gating.

STATUS2 (RO)

7:0

Default : -

Access : RO

HTT_CHG_CS

7

Htotal change in CSOG.

-

6

Reserved.

STD_PAL

5

0: NTSC.

1: PAL.

CSD

4

CSYNC Detected status.

0: Input is not CSYNC.

1: Input is detected as CSYNC.

INTM

3

Interlace / Non-interlace detecting result by this chip.

0: Non-interlace.

1: Interlace.

INTF

2

Input odd/even Field detecting result by this chip.

0: Even.

1: Odd.

IHSP

1

Incoming input HSYNC Polarity detecting result by this chip.

0: Active low.

1: Active high.

EFh

IVSP

0

Incoming input VSYNC Polarity detecting result by this chip.

0: Active low.

1: Active high.

CHIP_ID

7:0

Default : 0x00

Access : RO

F0h

CHIP_ID[7:0]

7:0

Chip id is 70h

CHIP_VERSION

7:0

Default : 0x01

Access : RO

F1h

CHIP_VER[7:0]

7:0

Version is 01h

-

7:0

Default : -

Access : -

F2h ~

F3h

-

7:0

Reserved.

TRISTATE

7:0

Default : 0x00

Access : R/W

-

7:5

Reserved.

OBBUS_TRI

4

Output bus Tristate.

VS_TRI

3

Output VSYNC Tristate.

HSY_TRI

2

Output HSYNC Tristate.

F4h

DE_TRI

1

Output DE Tristate.

Free Datasheet http://www.datasheet4u.net/

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