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MST703-LF Datasheet(PDF) 67 Page - List of Unclassifed Manufacturers |
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MST703-LF Datasheet(HTML) 67 Page - List of Unclassifed Manufacturers |
67 / 207 page ![]() Mstar Confidential for 深圳市江启科技有限公司 Internal Use Only MST703 Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0.1 - 67 - 11/24/2010 Copyright © 2010 MStar Semiconductor, Inc. All rights reserved. Scaler Register (Bank=00, Registers B0h ~ FFh) Index Mnemonic Bits Description VS2HS (RO) 7 Input VSYNC too close to input HSYNC. LN4_DETMD 6 4 Line Detect Mode for Hs, DE. HSTOL[5:0] 5:0 HSYNC Tolerance. 5: Default value. VSTOL 7:0 Default : 0x01 Access : R/W AUTONOSIGNAL_CLR 7 Set Auto-No-Signal status. AUTONOSIGNAL 6 Enable Auto-No-Signal function. HTT_FILTERMD 5 HTT Filter Mode. HVTT_LOSE_MD 4 HVTT Lose Mode. 0: Original. 1: New by WDT sample. E9h VS_TOL[3:0] 3:0 VSYNC Tolerance. 1: Default value. HSPRD_L 7:0 Default : - Access : RO EAh HSPRD[7:0] 7:0 Input Horizontal Period, count by reference clock. HSPRD_H 7:0 Default : - Access : RO - 7:5 Reserved. EBh HSPRD[12:8] 4:0 See description for HSPRD[7:0]. VTOTAL_L 7:0 Default : - Access : RO ECh VTOTAL[7:0] 7:0 Input Vertical Total Length, count by HSYNC. VTOTAL_H 7:0 Default : - Access : RO - 7:3 Reserved. EDh VTOTAL[10:8] 2:0 See description for VTOTAL[7:0]. PDMD2 7:0 Default : 0x60 Access : RW MCUCLK_SEL 7 MCU Clock Source Select. 0: XTAL. 1: MPLL divided. MCUDIV 6:4 MCU Clock divided by MPLL. 000: 4. 001: 6. 010: 8. 011: 10. 100: 12. 101: 14. 110: 16. EEh - 3:1 Reserved. Free Datasheet http://www.datasheet4u.net/ |
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