MST703-LF datasheet(66/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 66 -

11/24/2010

Scaler Register (Bank=00, Registers B0h ~ FFh)

Index

Mnemonic

Bits

Description

UHSP

3

User defined input HSYNC Polarity, active when IVSJ =1.

0: Active low.

1: Active high.

IHSJ

2

Input HSYNC polarity judgment.

0: Use result of internal circuit detection.

1: Defined by user (UHSP).

UINT

1

User defined non-interlace/interlace, active when INTJ = 1.

0: Non-interlace.

1: Interlace.

INTJ

0

Interlace judgment.

0: Use result of internal circuit detection.

1: Defined by user (UINT).

MDCTRL

7:0

Default : 0x00

Access : R/W

IP_TEST_MD

7:6

IP Test-bus selection.

VERR

5

Video CCIR656 Error correct.

0: Disable.

1: Enable.

Field_ABSMD

4

Field Postion Absolute Value Mode.

VFIV

3

Video Field Inversion.

0: Normal.

1: Invert.

VEXF

2

Video External Field.

0: Use result of internal circuit detection.

1: Use external field.

INTF

1

Interlace Field detect method select.

0: Use the HSYNC numbers of a field to judge.

1: Use the relationship of VSYNC and HSYNC to judge.

E5h

IFI

0

Interlace Field Inverting.

0: Normal.

1: Invert.

HSPW (RO)

7:0

Default : -

Access : RO

E6h

HS_PW

7:0

HS Pulse Width

VFREE

7:0

Default : 0x00

Access : R/W

AUTOOPCOAST_CLR

7

Set Auto-Coast-for-output status.

AUTOOPCOAST

6

Enable Auto-Coast-for-output.

E7h

MIN_VTT[5:0]

5:0

Minimum VTT to free-run.

E8h

HSTOL

7:0

Default : 0x05

Access : R/W

Free Datasheet http://www.datasheet4u.net/

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