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MST703-LF Datasheet(PDF) 64 Page - List of Unclassifed Manufacturers

Part # MST703-LF
Description  Small Size LCD TV Processor with Video Decoder
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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MST703-LF Datasheet(HTML) 64 Page - List of Unclassifed Manufacturers

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Mstar Confidential
for 深圳市江启科技有限公司
Internal Use Only
MST703
Small Size LCD TV Processor with Video Decoder
Preliminary Data Sheet Version 0.1
- 64 -
11/24/2010
Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
Scaler Register (Bank=00, Registers B0h ~ FFh)
Index
Mnemonic
Bits
Description
AUXCLK_GAT
5
0: Enable MVD MCU-support Clock.
1: Disable MVD MCU-support Clock.
CMBCLK_GAT
4
0: Enable MVD comb-filter Clock.
1: Disable MVD comb-filter Clock.
-
3
Reserved.
EOCLK_INV
2
External OSD sample Clock Inverting.
IDCLK_INV
1
Scaler input sample Clock Inverting.
FSCCLK_INV
0
Sub-carrier Clock Inverting.
PDMD1
7:0
Default : 0x00
Access : R/W
PDALL
7
All chip power down.
BIUCLK_GAT
6
0: Enable register interface clock.
1: Disable register interface clock.
OSDCLK_GAT
5
0: Enable OSD clock.
1: Disable OSD clock.
PCCLK_GAT
4
0: Enable CRT output suppot clock.
1: Disable CRT output suppot clock.
ADCCLK_GAT
3
0: Enable 3-channel ADC digital clock.
1: Disable 3-channel ADC digital clock.
VDCLK_GAT
2
0: Enable CCIR and MVD interface clock.
1: Disable CCIR and MVD interface clock.
IDCLK_GAT
1
0: Enable scaler clock.
1: Disable scaler clock.
E1h
FSCCLK_GAT
0
0: Enable MVD digital front-end clock.
1: Disable MVD digital front-end clock.
SWRST0
7:0
Default : 0x00
Access : R/W
REGR
7
Register Reset.
0: Normal operation.
1: Reset Register.
ADCR
6
ADC Reset.
0: Normal operation.
1: Reset ADC.
IPR
5
Digital Input Port Reset.
0: Normal operation.
1: Reset.
E2h
OP1R
4
Scaler Reset.
0: Normal operation.
1: Reset.
Free Datasheet http://www.datasheet4u.net/


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