MST703-LF datasheet(58/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 58 -

11/24/2010

Scaler Register (Bank=00, Registers B0h ~ FFh)

Index

Mnemonic

Bits

Description

YCDLYCTL

7:0

Default : 0x00

Access : R/W

LNBF4_MD

7

Four Line Buffer Mode.

VSD_PIPE

6

VSD Pipe select.

0: Original.

1: Early pipe 2 cycle.

-

5:3

Reserved.

C3h

YC_DLY_CTL

2:0

YC Delay Control.

000: Normal.

001: Y early 1 cycle.

010: Y early 2 cycles.

011: Y early 3 cycles.

100: Normal.

101: C early 1 cycle.

110: C early 2 cycles.

111: C early 3 cycles.

VTOTAL_MAX_L

7:0

Default : 0xFF

Access : R/W

C4h

TOTAL_MAX[7:0]

7:0

Vertical Max Total (lower 8 bits).

VTOTAL_MAX_H

7:0

Default : 0x07

Access : R/W

-

7:3

Reserved.

C5h

TOTAL_MAX[10:8]

2:0

Vertical Max Total (higher 3 bits).

-

7:0

Default : -

Access : -

C6h ~

C7h

-

7:0

Reserved.

ATGCTRL

7:0

Default : 0x00

Access : R/W

MAXR (RO)

7

Max value flag for Red channel (read only).

0: Normal.

1: Max value (255) value when AGR = 0.

Output over max value (255) when AGR = 1.

MAXG (RO)

6

Max value flag for Green channel (read only).

0: Normal.

1: Max value (255) value when AGR = 0.

Output over max value (255) when AGR = 1.

C8h

MAXB (RO)

5

Max value flag for Blue channel (read only).

0: Normal.

1: Max value (255) value when AGR = 0.

Output over max value (255) when AGR = 1.

Free Datasheet http://www.datasheet4u.net/

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