MST703-LF datasheet(57/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 57 -

11/24/2010

Scaler Register (Bank = 00, Registers B0h ~ FFh)

Scaler Register (Bank=00, Registers B0h ~ FFh)

Index

Mnemonic

Bits

Description

LINE_SHIFT

7:0

Default : 0x00

Access : R/W

-

7

Reserved.

SEL_V_CLR

6

Select Vcounter Clear by DOWNCNT_EQ1 or EARLY_VS.

-

5

Reserved.

VCR_FF_MODE

4

Enable output VSYNC follow input VSYNC mode.

FIELD_INV_VS

3

Line shift vs Field Inverse.

B0h

LINE_SHIFT_NUM[2:0]

2:0

Line Shift Numbers.

SYNC_CONTROL

7:0

Default : 0x08

Access : R/W

CLK_DLY[3:0]

7:4

Output clock delay select.

CLK_INV

3

Output Clock invert enable.

DE_INV

2

Output DE Invert enable.

VS_INV

1

Output VSYNC Invert enable.

B1h

HS_INV

0

Output HSYNC Invert enable.

SYNC_SEL

7:0

Default : 0x00

Access : R/W

-

7:4

Reserved.

SEL_VDE

3

Select VDE output to VSYNC pin.

SEL_HDE

2

Select HDE output to HSYNC pin.

B2h

DATA_SKEW

1:0

Bus data Skew select.

SVM_CLK

7:0

Default : 0x10

Access : R/W

-

7

Reserved.

GB_SWAP

6

Data Bus G, B Swap.

RG_SWAP

5

Data Bus R, G Swap.

SVM_CLK_INV

4

SVM Clock Inverse.

B3h

SVM_CLKDLY

3:0

SVM Clock delay select.

-

7:0

Default : -

Access : -

B4h ~

BFh

-

7:0

Reserved.

HSPRDL_L

7:0

Default : -

Access : RO

C0h

HSPRDL[7:0]

7:0

Number of system clock count at 512 HSYNCs.

HSPRDL_M

7:0

Default : -

Access : RO

C1h

HSPRDL[15:8]

7:0

Number of system clock count at 512 HSYNCs.

HSPRDL_H

7:0

Default : -

Access : RO

C2h

HSPRDL[23:16]

7:0

Number of system clock count at 512 HSYNCs.

Free Datasheet http://www.datasheet4u.net/

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