MST703-LF datasheet(31/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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31 / 207 page

Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 31 -

11/24/2010

Scaler Register (Bank=00, Registers 01h ~ 9Fh)

Index

Name

Bits

Description

LM_SWAP_8

0

Output Channel MSB LSB Swap in 8-bit bus mode.

DEBUG

7:0

Default : 0x00

Access : R/W

-

7

Reserved.

EOCK

6

Select External ODCLK.

-

5:4

Reserved.

PTEN

3

PLL Test register protect bit Enable.

0: Disable.

1: Enable.

87h

-

2:0

Reserved.

SL_CNTRL_1

7:0

Default : 0x00

Access : R/W

-

7:6

Reserved.

LIM_HS

5

Limit HSYNC period enable.

-

4:3

Reserved.

INT_CAP_EN

2

Interlace Capture Enable.

SHLN_FLD

1

Select Short Line Field.

88h

FRZ_SHLN

0

Stop Short Line Update.

SL_TUNE _1

7:0

Default : 0x70

Access : R/W

TNCOEF

7:5

Tune Coefficient.

89h

LCK_THRHD

4:0

Lock Threshold.

SL_TUNE_2

7:0

Default : 0x00

Access : R/W

8Ah

LMT_D5D6D7_H

7:0

Limit PLL_SET High byte.

SL_TUNE_3

7:0

Default : 0xC0

Access : R/W

8Bh

LMT_D5D6D7_L

7:0

Limit PLL_SET Low byte.

TARGET_SL_L

7:0

Default : 0x00

Access : R/W

8Ch

TARGET_SL_L

7:0

Target Short Line Low byte.

TARGET_SL_H

7:0

Default : 0x01

Access : R/W

8Dh

TARGET_SL_H

7:0

Target Short Line High byte.

-

7:0

Default : -

Access : RO

8Eh ~

8Fh

-

Reserved.

GAMMA_EN

7:0

Default : 0x00

Access : R/W

-

7:2

Reserved.

90h

ADR_INC_EN

1

Address Increase Enable.

0: Disable.

1: Enable.

Free Datasheet http://www.datasheet4u.net/

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