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MST703-LF Datasheet(PDF) 23 Page - List of Unclassifed Manufacturers

Part # MST703-LF
Description  Small Size LCD TV Processor with Video Decoder
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Mstar Confidential
for 深圳市江启科技有限公司
Internal Use Only
MST703
Small Size LCD TV Processor with Video Decoder
Preliminary Data Sheet Version 0.1
- 23 -
11/24/2010
Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index
Name
Bits
Description
SIVEND_L
7:0
Default : 0xEA
Access : R/W
4Ah
SIVEND[7:0]
7:0
Scaling Image window Vertical END (lower 8 bits).
SIVEND_H
7:0
Default : 0x00
Access : R/W
-
7:3
Reserved.
4Bh
SIVEND[10:8]
2:0
Scaling Image window Vertical END (higher 3 bits).
SIHEND_L
7:0
Default : 0xEA
Access : R/W
4Ch
SIHEND[7:0]
7:0
Scaling Image window Horizontal END (lower 8 bits).
SIHEND_H
7:0
Default : 0x01
Access : R/W
-
7:3
Reserved.
4Dh
SIHEND[10:8]
2:0
Scaling Image window Horizontal END (higher 3 bits).
VDTOT_L
7:0
Default : 0x00
Access : R/W
4Eh
VDTOT[7:0]
7:0
Output Vertical Total (lower 8 bits).
VDTOT_H
7:0
Default : 0x02
Access : R/W
-
7:3
Reserved.
4Fh
VDTOT[10:8]
2:0
Output Vertical Total (higher 3 bits).
VSST_L
7:0
Default : 0xEA
Access : R/W
50h
VSST[7:0]
7:0
Output VSYNC start (lower 8 bits).
VSST_H
7:0
Default : 0x00
Access : R/W
-
7:4
Reserved.
VSRU
3
VSYNC Register Usage.
0: Registers 20h – 23h are used to define output VSYNC.
1: Registers 20h and 21h are used to define No signal VSYNC.
Registers 22h and 23h are used to define minimum H total.
51h
VSST[10:8]
2:0
Output VSYNC start (higher 3 bits).
VSEND_L
7:0
Default : 0x06
Access : R/W
52h
VSEND[7:0]
7:0
Output VSYNC END (lower 8 bits).
VSEND_H
7:0
Default : 0x00
Access : R/W DB
-
7:3
Reserved.
53h
VSEND[10:8]
2:0
Output VSYNC END (higher 3 bits).
HDTOT_L
7:0
Default : 0x3C
Access : R/W DB
54h
HDTOT[7:0]
7:0
Output Horizontal Total (lower 8 bits).
HDTOT_H
7:0
Default : 0x00
Access : R/W
-
7:3
Reserved.
55h
HDTOT[10:8]
2:0
Output Horizontal Total (higher 3 bits).
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