MST703-LF datasheet(16/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 16 -

11/24/2010

Scaler Register (Bank=00, Registers 01h ~ 9Fh)

Index

Name

Bits

Description

DLYV

4

Analog Delay line for component analog Video input.

0: Delay 1 line.

1: Do not delay.

CSC_MD

3

Composite SYNC Cut Mode.

0: Disable.

1: Enable.

EXVS

2

External VSYNC polarity (only used when COVS is 1).

0: Normal.

1: Invert.

COV_SEL

1

Coast VSYNC Select.

0: Internal VSEP.

1: External VSYNC.

CADC

0

Coast to ADC.

0: Disable.

1: Enable.

COCTRL2

7:0

Default : 0x00

Access : R/W

11h

COST[7:0]

7:0

Front tuning.

00: Coast start from 1 HSYNC leading edge.

01: Coast start from 2 HSYNC leading edge, default value.

…

254: Coast start from 255 HSYNC leading edge.

255: Coast start from 256 HSYNC leading edge.

COCTRL3

7:0

Default : 0x00

Access : R/W

12h

COEND[7:0]

7:0

End tuning.

00: Coast end at 1 HSYNC leading edge.

01: Coast end at 2 HSYNC leading edge, default value.

…

254: Coast end at 255 HSYNC leading edge.

255: Coast end at 256 HSYNC leading edge.

VFAC_OINI

7:0

Default: 0x00

Access : R/W

13h

VFACOINI[7:0]

7:0

Vertical Factor Odd Initial value.

VFAC_EINI

7:0

Default: 0x80

Access : R/W

14h

VFACEINI[7:0]

7:0

Vertical Factor Even Initial value

-

7:0

Default : -

Access : -

15h

-

7:0

Reserved.

16h

INTCTROL

7:0

Default : 0x00

Access : R/W

Free Datasheet http://www.datasheet4u.net/

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