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MST703-LF Datasheet(PDF) 13 Page - List of Unclassifed Manufacturers |
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MST703-LF Datasheet(HTML) 13 Page - List of Unclassifed Manufacturers |
13 / 207 page Mstar Confidential for 深圳市江启科技有限公司 Internal Use Only MST703 Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0.1 - 13 - 11/24/2010 Copyright © 2010 MStar Semiconductor, Inc. All rights reserved. Scaler Register (Bank=00, Registers 01h ~ 9Fh) Index Name Bits Description VDS_EN 7 Input data double sample In CCIR input mode, 0: for horizontal output resolution less than 720 pixels. 1: for horizontal output resolution more than 720 pixels. In analog input mode, 0: half sample of input data. 1: original sample of input data. VDS_MTHD 6 Input data double sample Method. 0: Using average. 1: Using advance GT filter. IVDS 5 Input VSYNC Delay Select. 0: Delay 1/4 input HSYNC (recommended). 1: No delay. HES 4 Input HSYNC reference Edge Select. 0: From HSYNC leading edge, default value. 1: From HSYNC tailing edge. VES 3 Input VSYNC reference Edge Select. 0: From VSYNC leading edge, default value. 1: From VSYNC tailing edge. ESLS 2 Early Sample Line Select. 0: 8 lines. 1: 16 lines. VWRP 1 Input image Vertical Wrap. 0: Disable. 1: Enable. HWRP 0 Input image Horizontal Wrap. 0: Disable. 1: Enable. ISCTRL 7:0 Default : 0x10 Access : R/W DDE 7 Direct DE mode for CCIR input. 0: Disable direct DE. 1: Enable direct DE. DEGR[2:0] 6:4 DE or HSYNC post Glitch removal Range. 04h HSFL 3 Input HSYNC Filter. 0: Filter off. 1: Filter on. Free Datasheet http://www.datasheet4u.net/ |
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