MST703-LF datasheet(99/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 99 -

11/24/2010

Video Decoder Register (Bank = 02)

Index

Name

Bits

Description

HV_VTHRDSEL

5:4

00: 3/8 line.

01: 6/8 line.

10: 1.25 line.

11: 1.75 line.

As Threshold for V Extract.

HV_INTCNT

3:0

Composite SYNC Pixel Lengths Filter for V Extract.

V_POSTCOAST

7:0

Default : 0x00

Access : R/W

VCOST_FEXT

7:6

Coast forward control.

3Dh

VCOST_BEXT

5:0

Coast Backward control.

HV_SLICTRL

7:0

Default : 0x0C

Access : R/W

3Eh

HV_SLICTRL

7:0

HSYNC/VSYNC Slicer Control.

HV_HSLIOFSTHYS

7:0

Default : 0xC0

Access : R/W

HV_HSLIOFSTHYS

7:4

HSYNC slicer line Offset.

3Fh

AGC_FINE_LSB

3:0

AGC Fine gain (lower 4 bits).

PGA_CTRL1

7:0

Default : 0xC1

Access : R/W

PGA_AUTO

7

0: Manual PGA set by AGC_COARSE[1:0].

1: Auto PGA switch.

PGA_FSWT

6

0: PGA switch in VSYNC.

1: PGA switch in HSYNC.

AGC_COARSE

5:4

00: PGA x 1.

01: PGA x 2.

FREZ_CLMPDISBK

3

Freeze Clamp Function; VSYNC selection.

40h

SYNC_MAG_LOW_TH

2:0

If SYNC Magnitude is Low, Freeze HW Clamping 3 times.

PGH_TOP_TH

7:0

Default : 0xDA

Access : R/W

41h

PGA_TH_TOP

7:0

If AGC_FINE[11:0]>=16*PGA_TH_TOP[7:0], use smaller PGA and

16*PGA_H2L[7:0].

PGA_BOT_TH

7:0

Default : 0x40

Access : R/W

42h

PGA_TH_BOT

7:0

If AGC_FINE[11:0]<=16*PGA_TH_BOT[7:0], use larger PGA and

16*PGA_L2H[7:0].

AGC_CTRL1

7:0

Default : 0x14

Access : R/W

43h

-

7

Reserved.

Free Datasheet http://www.datasheet4u.net/

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