MST703-LF datasheet(94/207 Pages) ETC1

Part #	MST703-LF

Description	Small Size LCD TV Processor with Video Decoder

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94 / 207 page

Mstar Confidential

for 深圳市江启科技有限公司

Internal Use Only

MST703

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

- 94 -

11/24/2010

Video Decoder Register (Bank = 02)

Index

Name

Bits

Description

FSCPLL_MODE

7

0: External FSC Clock Mode.

1: Internal FSC Clock Mode.

ADC_DOUBLE

6

ADC Double Sample Rate Option.

REG_CLK_VD_VIP

5:4

00: 4 Fsc Clock on Digital.

11: 8 Fsc Clock on Digital.

REG_VCO_TYPE

3:2

10: VCO 16 Fsc.

01: VCO 8 Fsc.

00: VCO 4 Fsc.

REG_ADC_CLK_LAG

1:0

CLK_CC / CLK_ADC Phase Diff.

CSTATE_CTRL

7:0

Default : 0x86

Access : R/W

CTRL_MD

7:5

Default: 100b, Auto control mode.

-

4

Reserved.

18h

CTRL_STATE

3:0

State Stable State Value; default: 0110b.

MVDET_EN

7:0

Default : 0xC0

Access : R/W

MV_DETEC_EN

7

Microvision Detect Enable.

0: Disable.

1: Enable.

-

6:5

Reserved.

DSP_SYNC_ALW

4

Allow DSP to Control SYNC_FOUND.

DSP_APL_ALW

3:2

0: Allow DSP to Control APL_FREQ_IDEAL (Center Frequency).

19h

SECAM_MD

1:0

1: Allow DSP to Control APL_FREQ and APL_PHS (Full

frequency/PHS control).

SVD_EN

7:0

Default : 0x40

Access : R/W

SVIDEO_EN

7

0: Chroma Source from CVBS-Channel Input.

1: Chroma Source from C-Channel Input.

ADC_C_ALWY_ON

6

Chroma ADC 16Fsc-to-4Fsc Down-Sampling is Enabled.

1Ah

CLAMDSM_CTRL[15:10]

5:0

Clamping 12-bit Control code; integer parts.

BKLVL_FORCE1

7:0

Default : 0x80

Access : R/W

DISCLAMP3

7

HW Clamping frozen 3 times if SYNC magnitude is small.

CLMP_FREZ_ZERO

6

HW Clamping set to Zero when Frozen.

1Bh

CLAMDSM_CTRL[9:4]

5:0

Clamping 12-bit control code; fractional parts.

BKLVL_FORCE2

7:0

Default : 0xFF

Access : R/W

1Ch

CLMFZE_VRGE

7:0

Clamp Freeze of V Range.

VCR_VLSHT

7:0

Default : 0xFF

Access : R/W

1Dh

CLMFZE_HRGE

7:0

Clamp Freeze of H Range.

Free Datasheet http://www.datasheet4u.net/

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