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MST703-LF Datasheet(PDF) 93 Page - List of Unclassifed Manufacturers

Part # MST703-LF
Description  Small Size LCD TV Processor with Video Decoder
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MST703-LF Datasheet(HTML) 93 Page - List of Unclassifed Manufacturers

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Mstar Confidential
for 深圳市江启科技有限公司
Internal Use Only
MST703
Small Size LCD TV Processor with Video Decoder
Preliminary Data Sheet Version 0.1
- 93 -
11/24/2010
Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.
Video Decoder Register (Bank = 02)
Video Decoder Register (Bank = 02)
Index
Name
Bits
Description
STATUS1
7:0
Default : -
Access : RO
01h
READBUS1
7:0
Test bus 1.
STATUS2
7:0
Default : -
Access : RO
02h
READBUS2
7:0
Test bus 2.
STATUS3
7:0
Default : -
Access : RO
03h
READBUS3
7:0
Test bus 3.
STATUS_MUX
7:0
Default : 0x00
Access : R/W
04h
READBUS_CTRL
7:0
VIPTESTMUX Address Control of READBUS1, READBUS2, and
READBUS3.
-
7:0
Default : -
Access : -
05h ~
06h
-
7:0
Reserved.
DSP_ADD_PRT
7:0
Default : 0x00
Access : R/W
07h
DSP_ADD_PRT[7:0]
7:0
DSP register Address Port.
DSP_WDAT_PRT
7:0
Default : 0x00
Access : R/W
08h
DSP_WDAT_PRT[7:0]
7:0
DSP register Write Data Port.
DSP_RDAT_PRT
7:0
Default : -
Access : RO
09h
DSP_RDAT_PRT[7:0]
7:0
DSP register Read Data Port.
-
7:0
Default : -
Access : -
10h
-
7:0
Reserved.
COMB_LL_EN
7:0
Default : 0x00
Access : R/W
-
7:1
Reserved.
11h
APL_COMB_LL_EN
0
1: Mux to select Com Line Lock mode.
-
7:0
Default : -
Access : -
12h ~
13h
-
7:0
Reserved.
SOFT_RST
7:0
Default : 0x10
Access : R/W
SOFT_RST
7
1: Softrest AFEC modules.
14h
-
6:0
Reserved.
FPGA_CTRL
7:0
Default : 0xA8
Access : R/W
15h
FPGA_CTRL
7:0
Reserved for FPGA control.
REG_SOFT_RST2
7:0
Default : 0x00
Access : R/W
16h
REG_SOFT_RST2
7:0
Reserved for HW testing.
17h
CLK_CTRL
7:0
Default : 0xC9
Access : R/W
Free Datasheet http://www.datasheet4u.net/


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