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MST703-LF Datasheet(PDF) 91 Page - List of Unclassifed Manufacturers |
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MST703-LF Datasheet(HTML) 91 Page - List of Unclassifed Manufacturers |
91 / 207 page ![]() Mstar Confidential for 深圳市江启科技有限公司 Internal Use Only MST703 Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0.1 - 91 - 11/24/2010 Copyright © 2010 MStar Semiconductor, Inc. All rights reserved. Analog Register (Bank = 01) Index Name Bits Description WDT_LD 6 Watch Dog Timer Load Value by SW. WDT_EN 5 Watch Dog Timer Enable Bit. - 4:0 Reserved. WDT1 7:0 Default : 0x00 Access : R/W F1h WDT_WIDTH 7:0 Watch Dog Timer Width. WRLOCK0 7:0 Default : 0x00 Access : R/W WRLOCK0 7 Register lock (work with WRLOCK1). Register access is disabled when WRLOCK0 and WRLOCK1 are HIGH. Register access is enabled when WRLOCK0 and WRLOCK1 are LOW. F2h - 6:0 Reserved. PWMCLK 7:0 Default : 0x00 Access : R/W DB_EN 7 Double Buffer Enable. 0: Disable. 1: Enable. P2REN 6 PWM2 Reset every frame Enable. 0: Disable. 1: Enable. P1REN 5 PWM1 Reset every frame Enable. 0: Disable. 1: Enable. P2POL 4 PWM 2 Polarity when enhance PWM2 enable. EP2EN 3 Enhance PWM2 Enable. 0: Disable. 1: Enable. P1POL 2 PWM1 Polarity when enhance PWM1 enable. EP1EN 1 Enhance PWM1 Enable. 0: Disable. 1: Enable. F3h PCLK 0 PWM1/2 base Clock select. 0: 14.318MHz. 1: 14.318MHz / 4. PWM1C 7:0 Default : 0x00 Access : R/W PWM1_POL 7 PWM1 polarity. F4h PWM1_CTUN[6:0] 6:0 PWM1 Coarse adjustment. F5h PWM2C 7:0 Default : 0x00 Access : R/W Free Datasheet http://www.datasheet4u.net/ |
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