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EP1C12F100I7 Datasheet(PDF) 41 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 41 Page - Altera Corporation |
41 / 94 page ![]() Altera Corporation 41 Preliminary Information Cyclone FPGA Family Data Sheet Each PLL has one pre-scale divider, n, that can range in value from 1 to 32. Each PLL also has one multiply divider, m, that can range in value from 2 to 32. Global clock outputs have two post scale G dividers for global clock outputs, and external clock outputs have an E divider for external clock output, both ranging from 1 to 32. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered. External Clock Inputs Each PLL supports single-ended or differential inputs for source- synchronous receivers or for general-purpose use. The dedicated clock pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also act as LVDS input pins. See Figure 25. Table 11 shows the I/O standards supported by PLL input and output pins. For more information on LVDS I/O support, see “LVDS I/O Pins” on page 59. External Clock Outputs Each PLL supports one differential or one single-ended output for source- synchronous transmitters or for general-purpose external clocks. If the PLL does not use these PLL_OUT pins, the pins are available for use as general-purpose I/O pins. The PLL_OUT pins support all I/O standards shown in Table 11. Table 11. PLL I/O Standards I/O Standard CLK Input EXTCLK Output 3.3-V LVTTL/LVCMOS vv 2.5-V LVTTL/LVCMOS vv 1.8-V LVTTL/LVCMOS vv 1.5-V LVCMOS vv 3.3-V PCI vv LVDS vv SSTL-2 class I vv SSTL-2 class II vv SSTL-3 class I vv SSTL-3 class II vv Differential SSTL-2 v |
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