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EP1C12F100I7 Datasheet(PDF) 40 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 40 Page - Altera Corporation |
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40 / 94 page  40 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Table 10 shows the global clock network sources available in Cyclone devices. Notes to Table 10: (1) EP1C3 devices only have one PLL (PLL 1). (2) EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins CLK1 and CLK3. (3) EP1C3 devices in the 100-pin TQFP package do not have the DPCLK0, DPCLK1, or DPCLK5 pins. Clock Multiplication & Division Cyclone PLLs provide clock synthesis for PLL output ports using m/(n × post scale counter) scaling factors. The input clock is divided by a pre-scale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN × (m/n). Each output port has a unique post-scale counter to divide down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least-common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if the output frequencies required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the least-common multiple in the VCO’s range). Table 10. Global Clock Network Sources Source GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 PLL Counter Output PLL1 G0 vv PLL1 G1 vv PLL2 G0 (1) vv PLL2 G1 (1) vv Dedicated Clock Input Pins CLK0 vv CLK1 (2) vv CLK2 vv CLK3 (2) vv Dual-Purpose Clock Pins DPCLK0 (3) v DPCLK1 (3) v DPCLK2 v DPCLK3 v DPCLK4 v DPCLK5 (3) v DPCLK6 v DPCLK7 v |
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