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EP1C12F100I7 Datasheet(PDF) 36 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 36 Page - Altera Corporation |
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36 / 94 page  36 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Dual-Purpose Clock Pins Each Cyclone device except the EP1C3 device has eight dual-purpose clock pins, DPCLK[7..0] (two on each I/O bank). EP1C3 devices have five DPCLK pins in the 100-pin TQFP package. These dual-purpose pins can connect to the global clock network (see Figure 22) for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as TRDY and IRDY for PCI, or DQS signals for external memory interfaces. Combined Resources Each Cyclone device contains eight distinct dedicated clocking resources. The device uses multiplexers with these clocks to form six-bit buses to drive LAB row clocks, column IOE clocks, or row IOE clocks. See Figure 23. Another multiplexer at the LAB level selects two of the six LAB row clocks to feed the LE registers within the LAB. Figure 23. Global Clock Network Multiplexers IOE clocks have row and column block regions. Six of the eight global clock resources feed to these row and column regions. Figure 24 shows the I/O clock regions. Clock [7..0] Column I/O Region IO_CLK]5..0] LAB Row Clock [5..0] Row I/O Region IO_CLK[5..0] Global Clocks [3..0] PLL Outputs [3..0] Dual-Purpose Clocks [7..0] Global Clock Network Core Logic [7..0] |
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Similar Description - EP1C12F100I7 |
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