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EP1C12F100I7 Datasheet(PDF) 35 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 35 Page - Altera Corporation |
35 / 94 page Altera Corporation 35 Preliminary Information Cyclone FPGA Family Data Sheet Figure 22. Global Clock Generation Note (1) Notes to Figure 22: (1) The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7 ). (2) EP1C3 devices only contain one PLL (PLL 1). (3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. 8 Global Clock Network PLL1 PLL2 (2) CLK0 CLK1 (3) CLK2 CLK3 (3) DPCLK1 DPCLK0 DPCLK4 DPCLK5 DPCLK2 DPCLK3 DPCLK7 DPCLK6 2 2 From logic array From logic array 4 44 4 Cyclone Device |
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