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EP1C12F100I7 Datasheet(PDF) 32 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 32 Page - Altera Corporation

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Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 19. Input/Output Clock Mode in Simple Dual-Port Mode
Note (1)
Note to Figures 19:
(1)
All registers shown except the rden register have asynchronous clear ports.
Read/Write Clock Mode
The M4K memory blocks implement read/write clock mode for simple
dual-port memory. The designer can use up to two clocks in this mode.
The write clock controls the block’s data inputs, wraddress, and wren.
The read clock controls the data output, rdaddress, and rden. The
memory blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 20 shows a memory block in read/write clock mode.
6
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
D
ENA
Q
wraddress[ ]
address[ ]
Memory Block
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Data In
Read Address
Write Address
Write Enable
Read Enable
Data Out
outclken
inclken
inclock
outclock
wren
rden
6 LAB Row
Clocks
To MultiTrack
Interconnect
D
ENA
Q
byteena[ ]
Byte Enable
Write
Pulse
Generator


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