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EP1C12F100I7 Datasheet(PDF) 31 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 31 Page - Altera Corporation |
31 / 94 page ![]() Altera Corporation 31 Preliminary Information Cyclone FPGA Family Data Sheet Figure 18. Input/Output Clock Mode in True Dual-Port Mode Note (1) Note to Figure 18: (1) All registers shown have asynchronous clear ports. 6 D ENA Q D ENA Q D ENA Q data A[ ] address A[ ] Memory Block 256 × 16 (2) 512 × 8 1,024 × 4 2,048 × 2 4,096 × 1 Data In Address A Write/Read Enable Data Out Data In Address B Write/Read Enable Data Out clken A clock A D ENA Q wren A 6 LAB Row Clocks q A[ ] 6 data B[ ] address B[ ] clken B clock B wren B q B[ ] ENA AB ENA D Q ENA D Q ENA D Q D Q D ENA Q byteena A[ ] Byte Enable A Byte Enable B byteena B[ ] ENA D Q Write Pulse Generator Write Pulse Generator |
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