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EP1C12F100I7 Datasheet(PDF) 28 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 28 Page - Altera Corporation |
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28 / 94 page  28 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Byte Enables M4K blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 8 summarizes the byte selection. Notes to Table 8: (1) Any combination of byte enables is possible. (2) Byte enables can be used in the same manner with 8-bit words, i.e., in ×16 and ×32 modes. Control Signals & M4K Interface The M4K blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b , clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 15. The R4, C4, and direct link interconnects from adjacent LABs drive the M4K block local interconnect. The M4K blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 16 shows the M4K block to logic array interface. Table 8. Byte Enable for M4K Blocks Notes (1), (2) byteena[3..0] datain ×18 datain ×36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 – [26..18] [3] = 1 – [35..27] |
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