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EP1C12F100I7 Datasheet(PDF) 27 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 27 Page - Altera Corporation |
27 / 94 page ![]() Altera Corporation 27 Preliminary Information Cyclone FPGA Family Data Sheet Memory Configuration Sizes The memory address depths and output widths can be configured as 4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18 bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 6 and 7 summarize the possible M4K RAM block configurations. When the M4K RAM block is configured as a shift register block, the designer can create a shift register up to 4,608 bits (w × m × n). Table 6. M4K RAM Block Configurations (Simple Dual-Port) Read Port Write Port 4K × 12K × 21K × 4512 × 8256 × 16 128 × 32 512 × 9256 × 18 128 × 36 4K × 1 vvv v v v 2K × 2 vvv v v v 1K × 4 vvv vv v 512 × 8 vvv v vv 256 × 16 vvv v v v 128 × 32 vvv vv v 512 × 9 v vv 256 × 18 v v v 128 × 36 vv v Table 7. M4K RAM Block Configurations (True Dual-Port) Port A Port B 4K × 12K × 21K × 4512 × 8256 × 16 512 × 9256 × 18 4K × 1 vv vvv 2K × 2 vv vvv 1K × 4 vv v vv 512 × 8 vv vv v 256 × 16 vv v v v 512 × 9 vv 256 × 18 vv |
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